1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device with a complementary metal oxide semiconductor (CMOS) transistor.
2. Description of the Background Art
A CMOS transistor is a transistor where an NMOS transistor and a PMOS transistor are paired. A dual-gate electrode is a single continuous gate electrode used as a common gate electrode by the NMOS and PMOS transistors. The dual-gate electrode in an area for configuring the NMOS transistor is formed of N+ polycrystal silicon while the dual-gate electrode in an area for configuring the PMOS transistor is formed of P+ polycrystal silicon.
Conventionally, for a semiconductor device with the CMOS transistor, particularly for a semiconductor device with the CMOS transistor adopting the dual-gate electrode, only the entire region of the active region, the dual-gate electrode and the interconnection is selectively silicided to connect the N+ polycrystal silicon portion and the P+ polycrystal silicon portion in the dual-gate electrode with low resistivity, by using a technique of siliciding a high-melting-point metal in a self-aligned manner. An example is disclosed in Japanese Patent Laying-Open No. 59-107540.
Since the entire region of the active region, the dual-gate electrode and the interconnection is conventionally silicided, an insulating film of identical shape with the dual-gate electrode cannot be formed such that it covers an upper side of the dual-gate electrode after silicidation. Accordingly, such an insulating film cannot be used as a stopper film to form a contact hole in a self-aligned manner.
Additionally, when the entire active region is silicided with the technique of siliciding a high-melting-point metal, a problem such as abnormal silicidation often causes electrical leakage between the active region and the well. Therefore, silicidation of the active region is not desirable.